i/oZONE Products for the week of April 21, 2003
Aeluros says . . .
Cool Runnings - Aeluros 10 Gbit/s Serial Transceiver
Device Runs On Half The Power Of Competition
Puma Device Pushes the CMOS Envelope, Providing 10 Gbit/s
Serial-to-XAUI Capability for 10 Gbit/s Ethernet and Fibre Channel Applications
with Best-in-Class 800 mW Power Dissipation
Aeluros, a manufacturer of high-performance, low-power CMOS solutions, today introduced the Puma 10 Gbit/s-to-XAUI serial transceiver IC, the first product in its line of physical layer devices for the networking market. Using Hi-DensiPHY power reduction technology, Puma devices provide a typical power consumption of 800 mW, up to 60% less than currently available options. When combined with the inherent cost and integration advantages of CMOS process technology, this power reduction will enable new levels of edge density and will accelerate growth in the burgeoning 10 Gbit/s marketplace.
The 10 Gbit/s node represents a landmark convergence of physical layer implementations for datacom, storage and telecom systems. The rapid adoption of Gigabit Ethernet on the desktop and the growing dominance of 2-Gigabit Fibre Channel in the storage market are increasing bandwidth demands throughout the network. A variety of multi-source agreements (MSAs), including XENPAK, XPAK, and X2, define the implementation of 10 Gbit/s optical modules with a XAUI-based system interface. In addition, the XFP MSA, officially ratified earlier this year, brings 10 Gbit/s serial XFI signaling directly to the line card. Puma devices provide a low-power solution for both applications, addressing power and price constraints for module and system vendors alike.
"An optical transceiver module is a small, tightly enclosed space, and presents a challenging operating environment highly sensitive to thermal issues," said Osa Mok, Co-founder and Vice President of Marketing at Pine Photonics "Any module component able to offer a power savings of several hundred milliwatts or more will distinctly minimize this impact, greatly enhancing our ability to reliably maintain superior performance and eliminate extraneous cooling costs."
"The growth of 10 Gbit/s signaling will be driven by 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, and high port-count line cards," said Jag Bolaria, senior analyst at the Linley Group. "Low power is critical for increased linecard density, and Aeluros has set the mark for low power among 10 Gbit/s PHY suppliers."
Puma Device Details
Aeluros Puma devices provide a physical layer bridge between a 10.3125 Gbit/s or 10.51875 Gbit/s serial signal and a 4-lane, 3.125 Gbit/s or 3.1875 Gbit/s XAUI interface, including full implementation of 10 Gigabit Ethernet PCS/PMA functionality and support for both the IEEE 802.3ae 10 Gigabit Ethernet and INCITS 10 Gigabit Fibre Channel specifications. The 10 Gbit/s link provides a robust high-performance solution, and exceeds the 10 Gigabit Ethernet jitter requirements, while the XAUI interface is fully functional across a 40-inch FR4 backplane. The Puma device links have also been independently verified through successful interoperability with 10 Gigabit Ethernet LAN and XAUI performance modules from Ixia Inc as well as third party XENPAK optical transceiver modules.
Puma devices offer an extensive feature set including an integrated limiting amplifier with 10mV sensitivity, extended diagnostic and control signaling capabilities, and a flexible interface including multiple loopback modes and internal test pattern generation. Puma devices have full support for Revision 3 of the XENPAK specification, including support for Digital Optical Monitoring (DOM) registers. Puma devices provide a typical power consumption of only 800 mW, significantly below that of other available devices, and are housed in the small footprint of a 144-pin 13-mm x 13-mm BGA package.
Puma devices are also significantly cheaper to produce than competing products. They are manufactured in a mainstream digital CMOS process technology that does not require any specialized process options. Puma devices' low power consumption allows them to be packaged in an inexpensive wire-bond plastic BGA without the use of a heat spreader or other thermal enhancement.
Aeluros Technology
Puma devices are the first production device to be built using the Aeluros 10 Gbit/s links and Hi-DensiPHY power reduction technology. The Aeluros 10 Gbit/s implementation was developed via the previously announced Bobcat verification vehicle - the world's first quad channel 10 Gbit/s IC. The Bobcat device provided a serial link environment equivalent to a torture test of I/O and digital logic noise, and was verified both by the Aeluros team and by independent customer validation. The Puma product represents the culmination of a $5M investment in 10 Gbit/s serial technology that has enabled Aeluros to begin the methodical yet rapid deployment of a variety of 10 Gbit/s serial devices in a predictable, deterministic manner.
"The Aeluros Dream Team of mixed-signal talent continues to execute," said Richard Egan, CEO of Aeluros. "The Puma product provides all the performance at half the power of competing solutions. Aeluros has established a new benchmark and solved a real industry problem- this will provide a catalyst for new levels of integration density in all 10 Gbit/s markets."
analogZONE Says . . .
Even after a couple of years of seeing them on the market, I'm still having a hard time getting my head around 10-Gbit/s devices in CMOS - especially ones that run cleanly and with reasonable power consumption. But given the fact that Aeluros announced the world's first quad 10-Gbit/s single-chip CMOS device back in November 2002, (just after Transpectrum, my favorite dark horse, dropped out of the market) and it's now shipping, I have to take their recent announcement seriously.
The Aeluros Puma 10 Gbit/s-to-XAUI serial transceiver targets a wide
variety of applications in telecom, datacom, and even storage networks.
With all three areas converging on the 10-Gbit/s line standard, they are
betting in finding homes in the growing volumes of low-power optical modules
with small form factors, such as the XENPAK/X2/XPAK modules. It can also
can bridge XAUI-based devices to an XFP module.
To get around some of the power and speed issues, Aeluros takes a hybrid
digital/analog approach with digital control of analog functions that is
somewhat reminiscent of Silicon Labs and Cicada (which operates at much lower speeds.)
David Gamba, marketing director at Aeluros, says that regardless of what tricks you employ running a CMOS chip at 10 Gbit/s is not a picnic. It requires unique skills set to achieve multi-channel capability and the integration of digital logic. From what I can tell the design pushes but does not break the limits of vanilla CMOS at 0.013 micron. With an Ft of around 80 GHz at 0.13 micron, you have the absolute speed available, but the real issue is drain capacitance which gives you a resulting gate speed of 30 to 40 ps. Apparently the trick is to design logic that gives you at least 3 inverter delays per bit time if you want to do something meaningful.
Gamba says that it's relatively easy to get a 10-Gbit/s transceiver to work in CMOS, but quite tough to produce economically viable yields using standard foundry processes. To accomplish this their design measures the control current needed to lock the VCO and has digital mechanisms to calibrate other analog behavior on the chip - including limiting amplifier gains and CDR bandwidth.
In a very smart move, Aeluros verified the concept by spinning an early characterization chip. This allowed them to make sure their VCOs and other critical elements would have predictable, acceptable, jitter tolerance across a wide span of process variations. They applied extensive modeling and a rigorous "torture test" on the test article which included running it under temperature extremes with a wide variety of internal and external noise sources.
The result is that their "Puma" chip product has a very robust, stable CDR section that can handle data rates between 9.94 and 10.8 Gbit/s, allowing it to be used for darned-near every 10-Gbit/s transport standard, including 10G Ethernet at 10.3125 Gbit/s, 10G FiberChannel at 10.51875 Gbit/s, and the G.709 FEC ("Digital Wrapper") spec at 10.71 Gbit/s. It can also feed data to an XFI module at speeds of 9.95 to 10.75 Gbit/s.
The chip's XAUI SerDes interface is equivalent to many found on standalone backplane transceivers. It features both programmable transmit equalization and pre-emphasis (two taps for rise time, four bits for amplitude) that allows it to connect across 30 inches of FR-4 PCB, and four connectors. Although the transceiver's XAUI interface can support serial backplane applications, the marketing team is focusing on less cost-sensitive line card-side applications at first, and then moving to the backplane.
Aeluros recognized that keeping power consumption low was essential to allow designers to put lots of connections on a single power-limited line card. In truth, a typical line card blade can draw 50 - 60 W but, according to Aeluros, cooling at the edge of the blade becomes critical and results in typical limits of around 4 W per optical module.
Part of the designer's power management strategy involved reducing the power supply voltage for all internal circuitry to 1.2 V. Their other trick was to employ digital logic in nearly all low-frequency functions, and in high frequency functions whenever possible. Of course this approach requires exceptional noise immunity in the analog circuitry because of spikes coming from the digital circuits but, from what I can tell, the Aeluros design team seems to have been on top of the issue.
Thanks to this digital/analog hybrid CDR and control circuitry, power has been kept low - around 800 mW, about 35% to 50% that of competitors. All this compares very favorably with the 10Gbit/s transceiver recently released by Broadcom whose SerDes has a 12-inch reach, and a significantly higher power consumption.
The Puma is also a very full-featured, programmable part that can be configured to almost any application. You can access the chip via a standard interface to fiddle with the power management registers, enable one of several loop-back modes, or read the management interface support registers. You can even select XAUI link polarity inversion on a per-channel basis, making EMI control in PCB layout much easier.
For all its cool features, the Puma is a very compact chip at 2.5 mm by 5 mm. It is packaged in a plastic BGA but can still support full power dissipation at 85 degrees C.
Since the chip is small enough and draws so little power I expect it to end up as a core that is integrated to make multi-port chips or combined with other logic, such as a traffic manager, decoder, or other in-line processor.
I also like the fact that Aeluros has avoided "science fair syndrome"
by applying exhaustive design process and keeping its mouth shut until samples
were in the lab. The part gets big points with me by sampling now, with
production expected in Q4 2003. Pricing will be $150, in production quantities.
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