i/oZONE Products for the week of June 24, 2002
Agere says . . .
Gigabits Without Megabucks - Agere's SONET-Compliant
SERDES IP Adds OC-48 Connections To Your ASICS, While Cutting Power By Up
To 70 Percent
Agere Systems now has available a Synchronous Optical Network (SONET)-compliant Serializer/Deserializer (SerDes) sub-circuit that reduces power consumption of chip technology by approximately 70 percent and halves the number of silicon devices required per channel on a circuit board. These improvements enable an increase in overall system channel processing capacity by a factor of four or more compared with competing silicon offerings.
By integrating this SerDes into an Application Specific Integrated Circuit (ASIC), equipment manufacturers can directly connect Agere's ASICs to Agere's Netlight optoelectronic transceivers. For targeted line card applications, this system architecture adheres to the SONET 2.5 Gigabits per second (Gbits/s) Optical Carrier (OC)-48 standard. SONET OC-48 is a widely deployed communications transmission protocol for connecting voice, data, and video signal transmissions.
By integrating Agere's SerDes TSDR04 sub-circuit (macrocell) into Agere's ASIC chip, customers do not have to use a separate SerDes multiplexer/demultiplexer (mux/demux) chip or chips, as is the case with competing offerings. This integration lowers silicon costs and reduces the area used per port (per channel) in the same size system, thereby allowing an increase in SONET channel processing capacity on the same line card.
Agere's SerDes macrocell, a high-speed silicon interconnect sub-circuit, is integrated in a larger Agere ASIC system chip. A SerDes sub-circuit performs input and output functions that increase and decrease the transmission speed and reception of voice, data, and video signals through copper and fiber optic cables. SerDes sub-circuits are used widely in many types of data communications and telecommunications equipment including those equipped with SONET. Agere has integrated up to 64 channels of 2.5 Gbits/s SerDes on a single device.
By integrating the SONET-compliant TSDR04 SerDes macrocell onto the ASIC chip, Agere reduces the price per channel on a telecom line card by approximately $50 to $100. The TSDR04 chip technology also consumes 200 milliwatts per channel, approximately 70 percent less than competing SONET compliant silicon offerings. By integrating a single four-channel TSDR04 SerDes into an ASIC, customers eliminate four separate mux/demux devices from a four-port system, thus saving circuit board space and reducing cost.
"Agere's achievement enables equipment manufacturers to boost their system capacity while still using low-cost optoelectronics transceivers," said Beth Logan, strategic marketing manager with Agere Systems. "This is exactly what communications service providers want: to get more performance out of their existing infrastructures while minimizing overall system and electronics costs."
"There are very few companies that have the system-level know-how to understand the technical nuances of ICs and optoelectronics and make direct SONET compatibility work successfully," added Logan. "This achievement can broaden the deployment of high speed SONET connections, because it allows the use of low cost transceivers while meeting SONET specifications."
In addition to ASICs, Agere's family of SerDes macrocells have been used in the company's standard product designs and applications. For example, the macrocells have been integrated within network processors, switch fabrics, and traffic managers. SerDes macrocells within ASICs are used in various types of equipment such as routers, wireless base stations, and optical core and edge devices.
Agere is currently developing its fifth generation of SerDes macrocell. Three generations have been designed for speeds of 1 Gbits/s up to 3.3 Gbits/s. Agere's latest SerDes chips consume 82 milliwatts of power per channel at 3.125 Gbits/s. On a per channel basis, these latest chips are 40 percent of the size of the TSDR04 macrocell.
About NetLight
Agere's NetLight transceivers are high-speed, cost-effective solutions for
high-density data transport in metropolitan and access networks. Agere's
NetLight family consists of small-form-factor (SFF) pin-through-hole and
small-form-factor pluggable (SFP) transceivers at speeds from OC-3 (155
Megabits per second) to OC-48 (2.5 Gbits/s) as well as Gigabit Ethernet.
Agere's line of SFF transceivers offers the industry's most complete portfolio
of SONET/SDH-based devices, giving customers a single vendor to supply products
of all reaches and speeds to serve any market need.
Agere's SFP transceivers give systems makers the flexibility of designing
communications boards without the need to solder transceivers onto the board
during manufacturing, and service providers the option to "plug-in"
transceivers based on the speed or distance required.
analogZONE Says . . .
Agere has been in the SERDES business about as long as anyone else, and has come to understand the market and the technology well enough to accurately target markets with reliable, cost-effective products. In this case, they are making available an embedded SERDES core that allows your ASIC to enjoy the smaller footprint, lower power, reduced costs that only biggies like Broadcom and Marvell could boast until now.
Beth Logan, the core's product line marketing manager explained that there has been a traditional separation between the serial Mux/Demux for SONET applications and lower-powered SERDES devices that were intended mostly for backplanes which did not have such stringent jitter-compliance issues. Agere has worked hard at unifying the SERDES and Mux/Demux functions, combining the low jitter of SONET devices and the low power of backplane devices. Part of the effort was to make its own jitter measurement studies - no easy task because of conflicting opinions on what the specs mean at OC-48 and above.
Agere's TSER-03 macrocell has been tested as both a backplane SERDES and a SONET mux/demux. It is fully SONET compliant and this part works for both applications - a good thing. You should know that other Agere macrocells are also available that are somewhat lower power for backplane only applications.
The TSER-03 supports two speed ranges. It runs at half-rate from 1 to 1.6 Gbit/s, and at full-rate between 2.1 and 3.2 Gbit/s. This allows the versatile little beastie to be used for FiberChannel (full & half rate) links, plus the new quad 10-Gigabit FibreChannel spec. It also supports XAUI, and can run SONET over backplanes at 2.5 Gbit/s with 8B/10B coding. Ms. Logan declined to divulge details of how the PLL manages such a wide operating range with such tight specs, although she assured me that it works.
The cell can go directly onto a framer chip and has enough punch to directly drive an Agere 2.5 Gbit/s small form-factor NetLight medium haul transceiver with full SONET compliance. And speaking of punch, Agere says that it uses programmable pre-emphasis (0%, 12.5% or 25%), to enable the transceiver to drive up to 40 inches of FR-4 backplane with 2 connectors in the signal path. If you want to get exotic, it can also drive VCSEL-based optical backplanes.
The core's small size and power profile has allowed Agere to integrate high numbers (dozens) of SERDES on a single chip on an experimental basis with good success, and expects the same for its commercial customers. Agere supplies design rules and layout expertise to help integrate high lane density designs in the back-end part of the design cycle.
Power consumption is 200 mW/channel, a tad high in comparison for a backplane-only SERDES, but great for SONET-compliant parts. If it's really unacceptable, they have three new generations in the works that should take lower power. The first is a backplane-only element, expected to draw only 105 mW per channel. A newer generation will be available soon, that draws under 80 mW/channel at 2.5 Gbit/s, including all support circuits.
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