i/oZONE Products for the week of October 27, 2003
Accelerant says . . .
Fast, Flexible, & Forward-Looking -- Accelerant's
Binary DFE Transceiver Is Also Industry's Lowest-Power PAM-4 10-Gbit/s Backplane
Core At 0.22 W Per Link
0% overhead mode enables line rate OC-192 or 10GE per backplane
differential pair Binary Decision Feedback Equalization (DFE) interoperates
with legacy 1 - 5 Gbit/s SERDES
Accelerant Networks has announced availability of the highest performance, lowest power SERDES device available today for backplane applications. The AN6420 is the newest member of its AN6000 family of high-speed SERDES transceivers that offers breakthrough 0% overhead technology for the highest performance, lowest power SERDES device available, demonstrating line rates of 10 Gigabit payloads (Ethernet or OC-192) across existing backplane differential pairs, without increasing the existing power budget.
The device's four backplane interface cores require less than 870mW per 40 Gbits/s total payload, operating across FR4 material and two backplane connectors. This makes the AN6420 the highest performance, lowest power SERDES device available today for backplane applications.
The AN6420 operates at 6.25 Gigabits per second (Gbit/s) with a demonstrated rate up to 10 Gbit/s user payload in PAM4 multilevel signaling mode with no additional coding overhead (0 percent overhead), making it 25 percent more bandwidth efficient than typical 8B/10B coded transceivers. As with all Accelerant PAM4 transceivers, the AN6420 features adaptive equalization performed by the part. For interoperation in legacy binary modes with SERDES on existing line cards, the AN6420 operates up to 5 Gbits/s with a Decision Feedback Equalizer (DFE) in the receiver enabling it to offer robust operation independent of the quality of the legacy link.
For legacy upgrades the AN6420 includes the world's first binary backplane DFE implementation, allowing error-free operation at speeds up to 5Gbits/s even with eyes that are completely closed. This insures interoperability with the binary SERDES typical of the installed base of system line cards, enabling greater opportunities for system developers to upgrade existing network, server, and system chassis backplanes to higher performance.
"Maintaining a reasonable power budget, operating over low-cost interconnects, and interoperating with existing hardware have been the primary obstacles to upgrading existing backplanes to higher speed performance," said Bill Hoppin, vice president of marketing for Accelerant. "System developers have now designed Accelerant's AN6000 series into strategic upgrade projects that result in fundamental changes to product lifecycle at the system level. In addition, the technology is available now in an ASIC flow that provides the same functionality and power advantages of the discrete AN6420."
Many system vendors depend on ASIC integration to create key differentiation. Typically, technology available in the form of discrete merchant ICs has outpaced that available in ASIC cores by at least a generation. In backplane SERDES technology, power per user Gigabit is the ultimate metric when integrated as an ASIC core. The availability of Accelerant's leading edge, low power-per-user Gigabit technology both as a discrete IC and in an ASIC flow simultaneously is significant, as system developers will have greater design flexibility and cost-effectiveness both for today's upgrades and for tomorrow's next generation system designs.
The AN6420 is built with Accelerant's new modular development architecture
such that each building block can be re-used and optimized for custom applications
and integration into ASIC designs. Power consumption and die size of each
building block are extremely low, and are optimized for either backplane
interconnect or chip-to-chip applications. The 130nm AN6420 core is available
today from Agere Systems in its ASIC flow. Accelerant's building blocks
are also ideal for future cores integrated on 90nm CMOS optimized for further
improvements in die density and low power.
analogZONE Says . . .
With the introduction of its AN6420 Quad SerDes Transceiver, Accelerant seems to have mastered several critical strategic elements for easing a disruptive technology into a market that's already clogged with incumbents. Depending on your application the AN6420 can be configured as a four-channel, PAM4 backplane transceiver that can support data rates between 2 and 6 Gbit/s or 0.6 to 3 Gbit/s in binary mode. An internal quad 2:1 mux allows each channel to carry two complete XAUI, SONET, PCI-X, or FibreChannel data streams.
The device is a significantly-improved version of the AN6425 which was reviewed here this summer. Accelerant has already made its mark on the industry by championing multi-level (PAM) line coding technologies to increase the throughput of both backplanes and copper-based interconnects. In the process they have developed some unique signal analog processing techniques that have redefined what's possible. While not as groundbreaking as their earlier products, the refinements offered by the AN6420 should give it significantly improved performance and increased versatility that should win it sockets in many new designs -- as well as the all-important legacy retrofit market.
Like its earlier incarnations the AN6420 addresses the 1st order (tough) problems of performance and power, but it now also addresses more subtle secondary issues that make it a much more versatile part. Perhaps the most significant of these is interoperability with legacy hardware by falling back from PAM-4 mode to binary operation (jokingly referred to as PAM-2) on a per-channel basis. This allows an Accelerant-equipped switch fabric card or line card in a mesh system to be dropped into a backplane and communicate with the legacy cards while it waits for the other ends of the link to come up to speed. And even in binary mode, an Accelerant-equipped card may still improve overall system performance.
This is in part because the new chip packs an adaptive decision feedback equalizer (DFE) in the chip's receiver, a significant improvement over the earlier chip (the AN6425) which relied mostly on a sophisticated pre-emphasis and pre-distortion scheme to compensate for funky channel characteristics. The adjustable slicers on the earlier receiver were not really equalizers, and worked in PAM-4 mode only, (although they could still open up a 30 - 40 mV eye). The new receiver's decision-feedback equalizer (DFE) works in both binary and PAM modes. Besides improving performance, the DFE's digital control logic can collect statistics on channel performance and use them to perform blind equalization on a channel. Accelerant claims that you can routinely achieve bit error rates (BER) as low as 10E-30, even with a signal eye as low as 5 mV! This aggressive active equalization means that you can clean up marginal channels, where there is an Accelerant part on only one side of the line.
On the transmit side, the 6420's seven-tap adaptive pre-emphasis does not just blindly "spike" the beginning of a symbol to punch it up. Accelerant recognizes that over-reliance on pre-emphasis starts defeat itself by adding extra crosstalk to adjacent lines. The extra high energy from pre-emphasis also creates stronger reflections that distort the transmitters' outgoing symbols. To minimize these effects the Accelerant part calculates pre-emphasis levels on a per-symbol basis.
This flexibility allows the transceiver to operate in three distinct modes that can be used as most appropriate for your particular application.
The fully-adaptive mode uses an in-band signaling system between transmitter and receiver to adjust pre-emphasis and EQ settings in real time. In this dual-ended scenario, the chip "pings" the backplane on startup to determine its initial characteristics and then updates its values continuously.
If your channel characteristics don't vary rapidly (true in most applications), you can opt for a non-real-time adaptive scheme that passes parameters via an out-of-band link (using the on-chip MDC/MDIO interface) either through the host system or another serial channel). While the feedback path has a slower loop bandwidth, it should update quickly enough for most applications. This arrangement frees up capacity within the channel for more data at the expense of the system resources required to support the out-of-band channel. This is an excellent option for companies that already employ their own in-band signaling schemes for other purposes.
For many applications a fixed equalization scheme that uses derived tables is also a simpler and very adequate option. In this mode pre-emphasis values are downloaded from a table stored on the host system at startup. This is very useful where there is an Accelerant product on only one side of the line, or other situations where feedback from the receiver is not available.
And if this is not enough, there's an optional "0% overhead" mode that turns off the 8B5Q line coding normally used in the link. This frees up the 25% overhead it consumes. Accelerant claims this is possible because their 2nd generation scrambler guarantees there is signal sufficient transition density and dc balance to keep the receiver locked without the usual coding overhead.
Using the 0% overhead mode allows ordinary XAUI signal pairs to carry a full 5 Gbit of useful data each. Since no useless bits are shipped across the backplane, you can run your chassis at a lower effective speed. The result is that you require fewer mW-per-Gbit than almost any other solution. For example, a 6420 running all four 10-Gbit/s connections over a 30 inch FR-4 backplane consumes only 700 mW. I am not sure whether this mode will work under the more hostile line conditions found in some legacy applications, but it most certainly will have applications in fresh designs and more benign retrofits.
Between the chip's ability to make full use of channels with marginal conditions and support of both binary and PAM line coding, the AN6420 can be used to upgrade a wide range of legacy systems. Accelerant's VP of marketing, Bill Hoppin, claims that 90% of the market for 6 Gbit/s and higher speeds will be in upgrades for the next 2 years. While there is some dispute as to how much improving economic conditions will increase market share of new equipment, there are several major manufacturers who validate Hoppin's thesis. They are re-focusing their development efforts towards retrofitting their current products for added capacity and capabilities rather than rolling out new boxes. Besides saving major development and qualification efforts, this strategy also helps retain existing customers by giving them a cost-effective upgrade path.
But Accelerant is also looking ahead to a time when new designs will once again rule the market. They say their current chip demonstrates rock-solid operation at 10 Gbit/s (raw channel capacity), but is currently only guaranteed to 6.25 Gbit/s. This is a good indicator that they will be competitors in the 10-Gbit/s market as it matures.
Hoppin and crew also recognize that the market for stand-alone SerDes will be shrinking as the function becomes a commodity element within larger chips. Current estimates are that discrete SerDes products enjoy a 50% market share today, but that this will shrink to 30-40% by 2005. For this reason, Accelerant's design strategy has been to create their ASIC from lots of smaller, mix-and-match "Lego" modules. This makes their IP easily transportable to larger, more complex chips within Accelerant, as well as licensable by other companies.
They've also realized that their low-power solution will allow them to build products with higher channel densities as the market requires. To this end, their "overhead" support cores can be easily modified to control and monitor dozens, or even hundreds of channels. Apparently, the recent agreement with Agere to co-produce its own version of the earlier AN6425 is just a hint of things to come.
The AN6420 is in a 17 mm x 17 mm plastic BGA and is sampling now. It will be priced at $80 per unit in volume.
|