networkZONE Products for the week of June 7, 2004

Agere Systems Says . . .
UltraMapper & SuperPHY! Agere's Multi-Service Mapper/Managers, and Framer/PHYs Improve EoS Network Performance

Agere Systems has announced two breakthrough system-on-a-chip (SoC) product families that pave the way for wireline and wireless service providers to generate more revenues, by adding new and efficient service capabilities to their existing and next-generation access and broadband networks.

Agere's Datamapper and MARS T-PHY -- the world's most integrated mapper and framer chips respectively -- are versatile transport system chips for improving network performance and growing revenue-generating services. The chips help drive this growth particularly in fast-growing markets such as the online gaming and voice over Internet protocol (VoIP) markets.

Agere's Datamapper, which integrates more than 30 functions, is the world's first Ethernet-over-Synchronous Optical Network (SONET) mapper chip with integrated traffic management. This integration allows equipment vendors to slash costs by offering a six-fold reduction in software effort and a 50 percent reduction in mapping and traffic management silicon costs. Agere's massive integration enables the company's equipment customers to condense typical equipment used today, about the size of three stacked pizza boxes set side by side, down to one integrated system the size of one pizza box. The unmatched integration also enables service providers to converge wireless and wireline offerings within a single platform -- a major industry trend -- and thereby reduce their overall equipment and operational costs.

Similarly, Agere's MARS-T-PHY is the world's first framer family to combine a feature- rich, network-hardened 16-channel OC-3/OC-12 (155 Megabits per second [Mbits/s]/622 Mbits/s); four-channel OC-48 (2.5 Gbits/s); and single OC-192 (10 Gbits/s) framer with 16 multi-rate, auto detect clock and data recovery (CDR)/mux/demux physical layer interfaces (PHYs). These interfaces meet the most demanding SONET timing specifications. A software-compatible successor to Agere's groundbreaking MARS-T-Universal chip, this device continues to drive optical networking price per port, power per port, and line card density to new benchmark levels.

The integration offered by MARS-T-PHY reduces framer and clock silicon costs by approximately 30 percent. When combined with the auto rate detect feature in the integrated multi-rate CDR, the chip enables the design of a single equipment line card that supports all SONET/SDH rates. This consolidation reduces manufacturer's development costs and lowers service providers inventory-carrying and maintenance costs.

"The digital tsunami that will be hitting the broadband infrastructure due to on-line gaming in the next few years is shocking," said Eric Mantion, senior analyst with In-Stat/MDR. "Unlike web traffic, which can easily be mitigated by web caches, on-line gaming traffic goes right to a service provider's uplink and is extremely sensitive to even minor latencies [delays]. When tied to a similar surge in voice-over-Internet-protocol traffic, the next generation of networking gear for broadband providers will have to be more focused on traffic management and QoS than ever before.

"Luckily, Agere's two new SoC product families should allow network equipment providers to create just the right kind of solution at just the right time," he added. "The tremendous amount of integration found in these chips will allow the next generation of broadband gear to do everything they need to, while still being simpler in design than the previous generation.

On a single SoC, Datmapper combines the following major functions: a layer two processing engine and traffic manager; SONET PHY; framer; mapper; cross connect; data engine; virtual concatenation (VC); generic framing procedure-framed and transparent (GFP-F/T); media access controller (MAC); SPI-3 bus for connectivity to a co-processor; and high-speed SerDes (serializer/deserializer). Datamapper demonstrates the intelligence required to manage, organize and schedule different varieties of Quality of Service (QoS) levels. This functionality is similar in concept to a world-leading package delivery company that offers overnight, next day, first class, second class, and bulk delivery options, at different prices.

Using Agere's technology, for example, service providers can deliver the fastest, highest and most tunable bandwidth and highest-priority services to their premium service level customers, and lesser services at lower prices to others. In addition, Datamapper enables service providers to offer their top customers per-service guarantees for mission critical, time-sensitive services that cannot tolerate delays -- such as on-line gaming -- while allowing them to oversubscribe their networks to generate more revenue from more users.

"It often takes a revolutionary technology or radical change in thinking to enable the next step in the network evolution to occur," said Jonathan Reeves, president and CEO of Mangrove Systems. "By using Agere's Datamapper and MARS T-PHY system-on-a-chip solutions, Mangrove addresses a major industry challenge of extending Pseudowire, MPLS and Ethernet service delivery over SONET/SDH in the access and metro networks. Agere's technologies enable Mangrove to accomplish this using fewer silicon chips and lowering equipment costs, while improving the range of services that can be supported in a single converged platform."

Agere's new chips also accelerate deployment of smaller and less expensive Customer Premises Equipment (CPE) and Digital Subscriber Line (DSL) equipment and services into rural and remote areas. DSL has been slower to roll out in such areas compared with more metropolitan areas in part because equipment has been too large and expensive to deploy.

"Mangrove's selection of Agere's mappers with integrated traffic management and framers is particularly important to our company, because of Mangrove's intense focus, which Agere shares, on improving the economics, revenue-generating services, and reliability of leading next-generation access equipment," said Samir Samhouri, marketing director with the Agere Systems' Multiservice Networking Division.

analogZONE Says . . .

Ethernet over SONET (EoS) has become the buzzword, the mantra, and anticipated savior of the telecom industry, and Agere has launched a pair of products that should make this second coming of the all-IP future significantly less painful and expensive. But before we get going on reviewing these excellent products, I want to vent a bit and admit that I worry a bit that we're experiencing a bit of the pre-millennial-style hype that accompanied the Internet and network processors. While I agree that several very real factors have fueled a steady growth in the demand for bandwidth, there are still questions about how much of market growth is simply raw bandwidth, versus the VoIP and on-line gaming that require low-latency, deterministic IP services. And even if that demand is real, will it materialize anywhere near as quickly as the industry hype is claiming?

But even if you take the root-sum-square of the "irrational exuberance," it's clear that the conversion of the billions of dollars worth of SONET infrastructure to IP-based services is well underway. I'd also agree with Agere's claims that it's still hampered by cost and interoperability issues as we try to stitch together large networks with radically different underlying architectures and technologies. The two new Agere chip families should help ease this pain by using extremely high levels of integration to cut the cost and size of PoS equipment. The Datamapper family manages to combine all the functionality of an advanced mapper with a traffic manager, while the Mars T-PHY family sucks up the multi-rate framing tasks normally handled by a separate chip.

But this is not just a simple integration play. Agere seems to have done this right and used its ability to cram zillions of gates onto a chip to achieve significant gains in functionality and ease of implementation. This is most apparent in the Datamapper product line, where they appear to support all the important new standards that will make EoS services practical and efficient over metro, and even long-haul networks: this includes high and low-order VCAT/LCAS processing blocks provide low-order mapping down to the VT 1.5 level, but goes much further.

These mappers have the ability to aggregate and smooth out traffic flows to make the best use of available bandwidth without resorting to an external traffic manager, or, heaven forbid, network processor. This is because the on-chip layer-2 aggregation and buffer management logic allows multiple connections to be statistically multiplexed over a single VC group (see Mapper Block Diagram). When combined with the mapper's traffic management block, you get the ability to perform "precision over-subscription", and meter traffic from the Ethernet (24 10/100, or 4 GbE) connections into any number of 1.5 Mbit/s SONET VT groups you wish. And speaking of over-subscription, the same mechanisms allow the device to simultaneously process traffic coming from its four ten-bit interfaces and its SPI-3 bus as well as its Ethernet connections. This ability to efficiently use thin slices of bandwidth becomes increasingly important as you move closer to subscribers where the bursty traffic must be heavily groomed before being shipped across a TDM network.

The big payoff here is that providers should be able to carry different services on the same STS or STM connection because priority and QoS are handled in the "packet domain" before it is ever mapped into the SONET domain. I'm not quite ready to go out on a limb to say that this could not be done without Agere's on-chip traffic management, but I would say that it would likely be much more complex and expensive to do it another way.

The high levels of integration offered by these chips may go beyond simple linear improvements in the cost/performance ratio of access equipment and could give rise to equipment that causes disruptive changes in network topologies and service models. For example, they would make it rather easy to merge edge ADMs and DSLAMS, something that would eliminate the costly and cumbersome ATM layers currently used in most (North American) DSL systems.

SONET-enabled IP-DSLAMs would move SONET access further from the core and into the neighborhood, displacing the traditional ADMs and cross-connects we rely on today. Carriers would be able to enjoy the economies of IP services, but still offer latency-critical services such as telephony without breaking a sweat. And if you buy the notion that interactive games will drive much of the need for home bandwidth (I'm not sure I do -- at least in the U.S.), the low latency created by the tight coupling of the mapping and traffic management elements would be a real strategic advantage.

We could see similar changes in enterprises, since these chips could provide SONET access on the add-in blade of a router or switch, replacing more expensive CPE boxes.

While space does not permit as deep an analysis of Agere's MARS-T-PHY family, it's equally impressive. Like its companion mappers, it combines several complex functions that are usually found in two or three separate chips (see PHY Block Diagram). By integrating OC-3/OC-12/OC-48/OC-192 framing along with a highly flexible PHY, these devices cut the BOM cost and size requirements of any product needing to hook up to a SONET fiber.

Given Agere's expertise in carrier-class technologies and history of delivering on its promises, I think these two product families will make good on their claims of cutting the cost of SONET access. There are, however, a couple of questions remaining in my mind that will determine how much of the market they will capture.

First, I am not at all sure how the access market will be divided between these kinds of products and equipment supporting the WAN Interconnect Sublayer (WIS) standard that would be enabled by devices like the newly-announced QT2030 PHY (also reviewed this week). This will depend in part on how much dark fiber is available in a given region, and who owns it, as well as other imponderables such as the age of the installed equipment base.

The other factor that will govern the demand for these chips is whether carriers will really deploy the PoS services that require this sophisticated capability. As I hinted earlier, VDSL-based video delivery will probably remain a very speculative venture for the next 3 - 4 years, and I'm not completely sold on the idea that interactive gaming is going to be a market driver for low-latency residential connections -- but then again I'm pretty much of a Luddite in my personal life and don't even have cable in the house.

Putting any speculations on the size or timing of the market aside, these chips are impressive, both in their level of complexity and well-conceived architectures. This, and Agere's deep expertise in the intricacies of real-world SONET implementation should help equipment designers meet the demands of a rapidly-evolving market.

Agere is shipping both the Datamapper and MARS-T-PHY with the Datamaper priced from $250 to $500, depending on version, and the MARS-T-PHY from $402 to $680, both in 10-k piece lots.

Data Sheet - Datamapper
Data Sheet - MARS-T-PHY

Lee's Saltshaker Rating

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