networkZONE Products for the week of July 29, 2002
Agere Says . . .
One Chip Wonder - Agere Systems' 2.5 Gbit/s PayloadPlus
Network Processor Cuts Cost & Power In Routers, Switches, Access, 3G
Wireless Equipment
Industry's most integrated, cost- and power-efficient network
processor targets higher-density, high-performance networking and communications
equipment
Agere Systems Inc. has unveiled its second-generation PayloadPlus network
processor for high-performance deep-packet networking and communications
applications. Called INP5, the new product is a completely programmable
network processor capable of more functions, lower power consumption and
system cost than any competitive solution in its class. It is targeted to
original equipment manufacturers (OEMs) of multi-service edge platforms,
Internet protocol (IP) routers, digital subscriber line access multiplexers
(DSLAMs) and 2.5G and 3G wireless equipment.
Mounting economic pressures in the telecommunications industry have forced system builders to offer new products at comparatively lower prices than before with improved functionality and performance. The INP5 was specifically designed to meet the needs of network vendors in today's environment with the richest palate of functions and highest level of performance ever offered.
The industry's first single-chip network processor with full classification
and traffic management functionality, the INP5 enables higher port density
applications at line rates up to full-duplex OC-48c. With classification
and traffic management logic, 2.5 MB of internal RAM and integrated Ethernet
media access controllers (MACs), the INP5 can perform packet classification
with per flow policing and statistics, buffer management and packet scheduling
across 256k queues and extensive data modifications at full OC-48c line
rates for any packet size.
"The INP5's combination of flexibility, functionality and performance allows for building robust applications with extremely rich feature sets at lower costs than before," said Mark Pinto, vice president of the processing, aggregation and switching division at Agere Systems. "As a pioneer in the network processor space, Agere is the market leader in OC-48 carrier applications. The INP5 represents the culmination of Agere's unwavering focus on system-level solutions that increase performance, functionality and speed time-to-market, while reducing costs, power consumption and footprint."
"For example, the INP5's patented classification technology allows for high-speed table lookups with off-the-shelf DRAM, where competitors rely on expensive SRAM or even CAM (content addressable memory) devices," said Bill Klein, product marketing manager for network processors with Agere. "It can perform functions including per-flow service-level agreement (SLA) enforcement, tunnel origination and termination, access control lists (ACLs), hierarchical traffic shaping, and fabric and/or network packet segmentation, at full OC-48c rates, all while utilizing cost- and power-efficient DRAM technology."
"Network processors capable of handling the variety of protocols present at the network edge such as IP, ATM--including AAL2, frame relay and others--are most likely to gain a critical mass of customers because they are useful in a broader range of applications," said Joseph Byrne, communications ICs analyst with Gartner-Dataquest.
Based upon the same high-level programming model of Agere's PayloadPlus family, the INP5 also makes it easier for designers to develop value-added applications. Software-compatible with other members of the PayloadPlus network processor family, the INP5 is supported by Festino, a dramatically simplified software development environment. Festino also provides an easy feature-addition process along with reduced code maintenance costs.
About Festino
Agere's Festino hardware and software environment is the industry's most comprehensive platform of its kind, offering the broadest array of development options. It includes a software development environment (SDE), run-time environment (RTE) and scalable hardware development system (HDS) that includes support for Agere's 2.5 gigabits-per-second (Gbit/s) through 10 Gbit/s PayloadPlus network processors and Agere's protocol-independent PI-40 2.5 terabits-per-second (Tbit/s) switch fabric. Previously-written customer and third-party software will be compatible with the INP5 and Festino platform.
In addition, Agere has built alliances with numerous third-party software
vendors including Future Software, intoto, Hifn, Wind River Systems, Silicon
Software and Systems Ltd. (S3). "The Festino and third-party components
will enable customers to more quickly develop systems and applications on
the INP5," said Juan Garza, business development manager for Agere.
analogZONE Says . . .
It's no surprise that Agere's PayloadPlus network processors have been finding lots of acceptance in carrier-class equipment, and their new INP-5 processor should help them win even more sockets in the metro access and DSLAM market. Although not as fast as its bigger, multi-chip brother, the INP-10, the full-duplex, 2.5-Gbit/s INP-5 processor is a significant achievement because it cuts the parts count and cost of a full-up DSLAM, or multi-service switch by integrating many of its elements onto a single chip. In addition to the processor itself, the INP-5 incorporates a Fast Pattern Processor (FPP), Routing Switch Processor (RSP), and the Agere System Interface (ASI). Agere cuts costs further by incorporating large chunks of on-chip buffer RAM (almost 3 Mbytes), and a very slick classifier that uses inexpensive external DRAM instead of the pricey SRAM or CAM chips that are in common use (see the block diagram).
While many network processors were developed during the "IP-over-everything" craze, and have some challenges with TDM-based traffic, both INP-10, the INP-5 leverage Agere's extensive background in SONET/SDH to deliver deterministic switching, classification and traffic management services for TDM and ATM, as well as QoS-aware IP traffic. Since the product announcement above is pretty detailed about the features it supports, I won't elaborate on them here, but it seems that the INP-5 supports most important classification, management, and policing functions on a per-flow basis without running out of steam.
The processor is designed to interface directly to the Agere PI-40 switch fabric, which works much like an ATM switch insofar as it chops up anything passing through it into fixed-length cells and uses an appended tag to keep track of routing and latency management. While further details on the PI-40 are out of scope for this review, you can take peek at the its product brief by clicking here.
With a processor this complex, programming becomes the dominant element of a development cycle, so software and tools are an especially critical part of a product. Agere seems to be keenly aware of this, and had originally introduced its "Festino" development system for the INP-10. I took a closer look at the Festino system when I caught up with Agere at Supercomm this June, and was impressed at how complete and versatile it is. It has now been expanded to support the INP-5, and you can take a look for yourself at Agere's description of it by clicking here. If you cannot find the tools you need to tailor the INP-5 to your particular needs, there are several third-party vendors who will be happy to sell you protocol stacks, reference designs, and operating systems that will almost certainly give you what you need.
With all its embedded memory, this one-chip wonder is something like a large DRAM wrapped in a shell of processors and associated logic. Needless to say, this makes for a big, expensive chip. Nevertheless, the INP-5 incorporates so much functionality that it is a real bargain at around $800 for a typical OC-48 line card application. The power savings are also impressive at around 19 W for the same board - a real plus in cramped DSLAMs, telco racks and cellular equipment cabinets.
This is an ambitious chip, even for the likes of Agere, but since the INP-10 is already running, their delivery dates seem to be at least close to realistic. Their experience in large SOCs, and successful delivery of equally complex network processing chips earns them a low Vapor Index Rating.
The INP5 will sample in Q4 2002 in 133-MHz and
266-MHz versions, with volume pricing at $295 and $590 respectively.
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